1. Field of the Invention
The present invention relates to a semiconductor device in which a plurality of LSIs are stacked.
2. Background Art
So far, with the advancement of microfabrication technology, the performance improvement and functional upgrade of LSIs have been achieved by integrating more transistors in a single chip. However, due to the effects of the limits of miniaturization and the increases in the cost of utilizing state-of-the-art processes, performance improvement by means of integration into a single chip as practiced so far may not be a best solution in the future. Accordingly, three-dimensional integration by stacking a plurality of LSIs will be a promising technology. With this being the case, communication technology between LSIs to be stacked and between stacked LSIs and the outside thereof will become critical. As such a communication scheme, wired schemes based on solder bumps, through silicon via, etc. and wireless schemes are being studied.
While in the media processing and network processing in recent years, the amount of data to be transferred between a processor LSI including a CPU, etc. and a memory LSI has been increasing year by year, there is a demand for increasing the communication traffic volume therebetween and for reducing the power consumed by the communication. Under such circumstances, a method of decreasing the communication distance by stacking those LSIs has been contemplated. JP Patent Publication (Kokai) No. 2002-231880 refers to a configuration in which three LSIs, that is, a processor LSI incorporating a nonvolatile memory, a nonvolatile memory LSI, and a volatile memory LSI are stacked on top of one another, suggesting that the storage capacity in total can be increased, and further operation at a higher speed is possible.